1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to circuitry that forms a communications "bridge" between components in a personal computer system. Still more particularly, the present invention relates to a bridge logic device that includes an internal modular expansion bus for facilitating the transfer of data between an internal master device and other computer system components operating under a different protocol.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modern computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. One of the critical requirements in designing a new computer system is that all system components (including those which may be added to the system by a user) must be compatible. A component is compatible if it effectively communicates and transfers data without interfering or contending with the operation of other system components. Because modern computer systems are designed with components that operate with different protocols, the likelihood that components may not properly communicate is heightened. Compatibility between devices with different protocols is achieved with bridge logic devices. As the name implies, bridge logic devices provide a communications bridge between components and busses operating under different protocols. The present invention is directed to an improved bridge logic device. Computer systems have components with different protocols because of the manner in which computers evolved, and the desire to make new computer designs backwards-compatible with prior designs. This backward compatibility insures that the user can use a peripheral device from a prior computer in a new computer system.
Early computer systems had relatively few components. As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a "bus." As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by including the peripheral device on the main system circuit board (or "motherboard") and connecting it to the system bus.
The computer operates by having data flow through the system, with modification of the data occurring frequently. Typically, the CPU controls most of the activities of the computer system. The CPU supervises data flow and is responsible for most of the high-level data modification in the computer. The CPU, therefore, is the heart of the system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
The performance of the computer system is determined only in part by the performance of the processor. Other factors also affect performance. One of the most critical factors is the bus that interconnects the various system components. The size and clock speed of the bus dictate the maximum amount of data that can be transmitted between components. One early bus that still is in use today is the ISA (Industry Standard Architecture) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with computer systems of most computer companies. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A number of peripheral components have been developed over the years to operate with the ISA protocol.
Since the introduction of the ISA bus, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and both processor speeds and the size of memory arrays have increased dramatically. In conjunction with these advances, designers have sought to increase the ability of the system bus to transfer more data at a faster speed. One way in which system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, however, a new bus protocol had to be developed. One such bus that permits peripheral devices to run cycles independently of the CPU as a "master" device is the EISA (Extended Industry Standard Architecture) bus. The EISA bus enables various system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus. Another bus that has become increasingly popular is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus has bus master capabilities. The PCI bus also operates at a clock speed of 33 MHz or faster.
Because of the bus mastering capabilities and other advantages of the PCI (and EISA) bus, many computer manufacturers now implement one or the other of these busses as the main system bus in the computer system. Because of the proliferation of devices that had been developed for the ISA bus, the computer manufacturers also continued to provide an ISA bus as part of the computer system to permit the use of the many peripheral devices that operated under that protocol. To further provide flexibility, some computer manufacturers provide all three busses in the same computer system to permit users to connect peripheral devices of all three protocols to the computer system. To implement these various busses in the same computer system, special bridge logic circuit has been developed to interface to the various busses.
FIG. 1 shows a representative prior art computer system that includes a CPU coupled to a bridge logic device via a CPU bus. The bridge logic device is sometimes referred to as a "North bridge" for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
If other expansion busses are provided in the computer system, another bridge logic device typically is used to couple the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a "South bridge" reflecting its location vis-a-vis the North bridge in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation. In FIG. 1, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus.
As one skilled in the art will understand, devices residing on the ISA bus may need to run cycles to memory via the PCI bus. The PCI bus permits devices residing on the PCI bus to run master cycles to targets residing on the PCI bus. To permit devices on other busses to run master cycles on the PCI bus, the controller for that device must be included in the South bridge logic. This controller then would be responsible for converting the signals from other busses to PCI signals for master cycles. Thus, the controller for the ISA device, for example, must understand the protocol of both busses. As an example, if the designer wanted to permit the modem to run master cycles on the PCI bus in FIG. 1, then an associated controller would be provided in the South bridge logic that was capable of asserting master signals on the PCI bus and translating ISA signals to PCI signals. If the modem also could be a target for PCI cycles, the controller in the South bridge also has to be capable of accepting PCI cycles and converting the PCI cycles to ISA cycles. Similarly, if the hard drive could also function as a PCI master, then an associated controller must also be provided in the South bridge logic to assert master signals on the PCI bus and receive and process PCI signals from other masters.
One of the problems with this technique is that when the destination bus for internal masters changes, all the internal masters must be redesigned. Further, the destination bus interface for internal masters requires numerous modifications when adding additional masters. Also, the internal masters are more complex than required to understand the expansion bus protocol. In addition, every time that another expansion device is added, the South bridge logic must be re-designed to include a PCI controller for that device. Similarly, every time that the expansion bus changes or is replaced with a different design, then the entire South bridge logic must be re-designed. Also, the South bridge must be designed in a manner to insure that two controllers within the South bridge do not both assert mastership signals at the same time causing bus contention problems. To date, no one has developed a bridge logic device that overcomes these deficiencies.